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Class for generating verilog, bitstreams, and running simulations

Hierarchy

  • CodeGenerator

Index

Constructors

constructor

Properties

m

the working module

Methods

buildBitstream

  • buildBitstream(projectName: string, cleanupIntermediateFiles?: boolean): Promise<void>
  • Compiles CodeGenerator.m to verilog, performs synthesis, routing, and creates a bitstream

    Parameters

    • projectName: string

      the name of the project (generated files will use this name)

    • Default value cleanupIntermediateFiles: boolean = true

      if true, the files generated during compilation, synthesis, and routing will be removed

    Returns Promise<void>

runSimulation

  • runSimulation(projectName: string, vcdFile?: string, cleanupIntermediateFiles?: boolean): Promise<void>
  • Compiles CodeGenerator.m to verilog as if it were a simulation, creating an associated VCD wave file if provided Cleans up all associated files after simulating, except the VCD

    Parameters

    • projectName: string

      the name of the project (generated files will use this name)

    • Optional vcdFile: string

      the name of VCD wave file to generate

    • Default value cleanupIntermediateFiles: boolean = true

    Returns Promise<void>

toVerilog

  • toVerilog(): string

writeVerilogToFile

  • writeVerilogToFile(projectName: string): Promise<void>
  • Compiles CodeGenerator.m to verilog and writes it to a file

    Parameters

    • projectName: string

      the name of the project (generated files will use this name)

    Returns Promise<void>

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