Creates a new CodeGenerator
top level module
configuration options
the working module
Compiles CodeGenerator.m to verilog, performs synthesis, routing, and creates a bitstream
the name of the project (generated files will use this name)
if true, the files generated during compilation, synthesis, and routing will be removed
Compiles CodeGenerator.m to verilog as if it were a simulation, creating an associated VCD wave file if provided Cleans up all associated files after simulating, except the VCD
the name of the project (generated files will use this name)
the name of VCD wave file to generate
Compiles CodeGenerator.m to verilog
Compiles CodeGenerator.m to verilog and writes it to a file
the name of the project (generated files will use this name)
Generated using TypeDoc
Class for generating verilog, bitstreams, and running simulations