Options
All
  • Public
  • Public/Protected
  • All
Menu

Module "main-types"

Index

Enumerations

Type aliases

Type aliases

BlockStatement

BlockStatement: LogicStatement | AssignmentStatement

CaseExpression

CaseExpression: SubjectiveCaseStatement | DefaultCaseStatement

CombinationalLogic

CombinationalLogic: AssignmentStatement | CombinationalSwitchAssignmentStatement

Various kinds of combinational assignments that can be made

LogicStatement

LogicStatement: IfStatement<SignalLike, BlockStatement> | ElseIfStatement<SignalLike, BlockStatement> | IfElseBlock<SignalLike, BlockStatement> | SwitchStatement

Logic expressions can only be used in synchronous blocks

ParameterString

ParameterString: { type: "parameterString"; value: string }

Type declaration

  • type: "parameterString"
  • value: string

Port

Port: SignalT | WireT

Any kind of connectable interface

SignalLike

SignalLike: BaseSignalLike | SignalT | WireT | SliceT | ConcatT | Inverse | UnaryT | ComparrisonT | ConstantT | BinaryT | TernaryT | BooleanExpressionT | ExplicitSignednessT | SignalArrayMemberReference

Anything that can be treated as if it were a SignalT

SignalLikeOrValue

SignalLikeOrValue: SignalLike | number

Like SignalLike except allows for numbers (issues will occur if non-integers are used) Likely to be removed in the future.

SimulationExpression

SimulationExpression: BlockStatement | EdgeAssertion | RepeatedEdgeAssertion | DisplayExpression | FinishExpression | IfStatement<SimulationSignalLike, SimulationExpression> | ElseIfStatement<SimulationSignalLike, SimulationExpression> | IfElseBlock<SimulationSignalLike, SimulationExpression> | SimulationAssignmentStatement

Any valid expression within a simulation

SimulationSignalLike

SimulationSignalLike: SignalLike | SubmodulePathT

Regular SignalLikes, plus SignalLike types that can only be used in simulation

SubmodulePortMappping

SubmodulePortMappping: { inputs: {}; outputs: {} }

Type declaration

Generated using TypeDoc